1. Field of the Invention
The present invention relates to a method of driving a display panel having an active matrix base plate and, more particularly, to a method of driving a liquid crystal display panel for displaying a multivalue image such as a television image or the like.
2. Related Background Art
Hitherto, there has been proposed a display panel for displaying a multivalue image, for example, a television image by use of a high density two-dimensional matrix type liquid crystal panel (active matrix type liquid crystal panel) using a thin film transistor (hereinafter, abbreviated to a TFT).
Such a display panel is constituted as shown in, for example, FIG. 3. As a method of driving such a display panel, there has already been proposed a system in which an image signal which is applied to the panel is inverted for the period of integer times, in particular, one time as long as one horizontal scanning period. In FIG. 3, reference numeral 1 denotes an image signal input terminal; 2 is an amplifier to amplify the input image signal; 3 denotes an inverter to invert and amplify the amplified image signal; 4 denotes a switch to change over the outputs of the amplifier 2 and inverter 3 in accordance with the polarity of the signal which is derived by frequency dividing a vertical sync signal, which will be explained hereinafter, by half; T.sub.1 to T.sub.m denote switches to distribute the signal switched by the switch 4 to capacitors C.sub.1 to C.sub.m by control signals H.sub.1 to H.sub.m, respectively; S.sub.1 to S.sub.m denote source lines of a liquid crystal panel 11 which is connected to the capacitors C.sub.1 to C.sub.m ; G.sub.1 to G.sub.n denote gate lines of the liquid crystal panel 11; LC.sub.11 to LC.sub.nm denote pixels of the liquid crystal panel; 5 denotes a horizontal sync signal (HD) input terminal; 6 denotes a clock generator to generate the clock signal which is substantially m times the HD in rate; 7 denotes a horizontal shift register to sequentially generate the scanning pulses H.sub. 1 to H.sub.m synchronized with the HD in response to the output of the clock generator 6; 8 denotes a vertical sync signal (VD) input terminal; 10 denotes a vertical shift register for shifting at the HD period and for sequencially generating scanning pulses synchronized with the VD; 20 denotes a frequency divider (I) for frequency dividing the HD by half; 21 a frequency divider (II) for frequency dividing the VD by half; and 22 denotes a pulse distributing circuit for generating a pulse to set/reset the frequency divider (I) 20.
In the foregoing driving circuit, an image signal such as, for example, a television signal is input to the image signal input terminal 1 and amplified by the amplifier 2 to a signal amplitude which is suitable to drive the liquid crystal. The amplified image signal is supplied to the switch 4 and inverter 3. The switch 4 selects the outputs of the amplifier 2 and inverter 3 in accordance with the polarity of the output signal of the frequency divider (I) 20, which will be explained hereinafter, in order to produce the image signal. This switching operation is needed to drive the liquid crystal in an alternate current manner. The image signal is supplied to the common terminals of the switches T.sub.1 to T.sub.m and distributed to the capacitors C.sub.1 to C.sub.m and to the source lines S.sub.1 to S.sub.m connected thereto in response to the control signals H.sub.1 to H.sub.m. The clock signals which are generated from the clock generator 6, and are substantially m times the horizontal scanning interval, are is supplied to the horizontal shift register 7, and the scan is sequentially performed for one horizontal period by the control signals H.sub.1 to H.sub.m. By sequentially making the switches T.sub.1 to T.sub.m conductive for only one clock period, the image signals respectively corresponding to pixels LC.sub.kl to LC.sub.km (K=1 to n) in the horizontal direction are sampled and held in the capacitors C.sub.1 to C.sub.m. One of the gate lines G.sub.1 to G.sub.n is turned on during the horizontal blanking period of the image signal, and the signals sampled and held in the capacitors C.sub.1 to C.sub.m are transferred to the pixels LC.sub.kl to LC.sub.km of one line and displayed. The signals such as to sequentially scan the gate lines G.sub.1 to G.sub.n within one vertical scanning interval in which the HD is used as the clock are generated from the vertical shift register 10 and applied to the gate lines G.sub.1 to G.sub.n. FIG. 4 shows a timing chart for this operation.
With the above constitution, a television image is displayed on the liquid crystal panel 11.
As mentioned above, the frequency divider (I) 20 frequency divides the HD by half, and the image signal is controlled by a polarity inverting circuit consisting of the inverter 3 and switch 4. The set/reset signal generated from the frequency divider (II) 21 and pulse distributing circuit 22 is supplied to the divider (I) 20. The set/reset signal is constituted such as to alternately and repeatedly set and reset at every VD period. Therefore, the phase of the output of the divider (I) 20 is inverted at every VD period.
By use of the above-mentioned circuit, the signal whose phase is inverted at every VD can be applied to a COM for the period which is shorter than 1VD and is integer times as long as 1HD.
FIG. 5 is a constitutional diagram showing an example of the pixels LC.sub.11 to LC.sub.nm. In FIG. 5, reference numeral 12 denotes a TFT; 13 denotes a leak resistor of a TFT; 14 denotes a liquid crystal cell; and 15 denotes a common opposite electrode (ITO) of the liquid crystal cell. The signal which is obtained by sampling and holding the image signal is supplied as the source signal S of the TFT 12. The vertical scanning signal is supplied to a gate line G. While the gate line G is ON, the source S and drain D of the TFT 12 are made conductive and the voltage of the source line S is applied to the capacitance C.sub.LC of the liquid crystal cell 14. Thus, the waveform of the capacitance C.sub.LC becomes the AC driving waveforms which are inverted at every vertical period as shown at V.sub.LCll and V.sub.LCln in FIG. 4.
FIG. 6 is a characteristic graph showing the relation between the driving voltage of the liquid crystal and the transmission factor. The abscissa axis indicates the voltage between both terminals of the liquid crystal and the ordinate axis represents the transmission factor of the liquid crystal. In the graph, V.sub.1 and V.sub.2 denote voltage threshold values at the start and end of the phase transition. In general, the transmission factor of the liquid crystal does not change at voltages within a range of 0 to V.sub.1 but changes in correspondence to the voltage within a range of V.sub.1 to V.sub.2. Therefore, the image signal is supplied at voltages within a range of V.sub.1 to V.sub.2 and the voltage amplitude of the signal falls within the range of 0 to V.sub.2.
According to the above-mentioned conventional method, the voltage value of the signal which is applied to the source line becomes ten-odd volts. However, on the other hand, a CMOS integrated circuit is used as the driving circuit of the source line in order to reduce the electric power comsumption. The CMOS integrated circuit can operate at a voltage of tenodd volts and its operating speed is limited to 2 to 3 MHz. Therefore, in the case of driving the display panel of a high fine pitch, for example, 640.times.400 pixels at a driving frequency of about 12 MHz, the driving circuit cannot be realized as a CMOS-IC.